Semiconductor structures, such as layers, substrates, wafers and wells, can have a particular type of conductivity (e.g., p-type, n-type). Within that structure, wells having an opposite type of conductivity (e.g., N-wells, P-wells) can be formed. Complementary metal oxide semiconductor (CMOS) devices can be formed using such structures. Such devices can be used as, for example, support circuitry in memory devices.
CMOS devices can typically be formed as relatively low voltage or relatively high voltage devices. For example, the high voltage devices might be biased at voltages greater than 30V while low voltage devices might be biased at voltages less than 5V.
N-wells in a p-type structure form a p-n junction at the interface of the well with the structure. FIG. 1 illustrates a cross-sectional view of a typical p-n junction. This figure shows an N-well 101 formed within a p-type structure 100. An N-well contact 102 is coupled to a heavily doped N+ tap 104 that is formed relatively close to the edge of the well 101 at the illustrated distance 110.
A p-type isolation area 120 can be formed in the semiconductor material that forms the bottom surface of a trench between two taps 104, 105. The isolation area 120 can provide isolation between neighboring n-channel devices.
Biasing a p-n junction at too large of a voltage can cause the junction to breakdown and start conducting. When a voltage is applied to the N-well contact 102 that is greater than the designed breakdown voltage for the device, the p-n junction 130 breaks down at the interface of the p-n junction with the isolation area 120.
There are resulting needs for increasing this breakdown voltage.